The present invention relates to multi-core integrated circuits, and, more particularly, built-in-self-testing (BIST) circuitry for multi-core integrated circuits.
Multi-core integrated circuits (IC) include multiple processor cores that execute the same or different functions in cohesion. Certain multi-core ICs include two or more processor cores with each processor core executing a different function. Such multi-core ICs are known as heterogeneous multi-core ICs. For example, a heterogeneous multi-core IC may have a first processor core that is a general purpose processor and a second processor core that is a digital signal processor (DSP).
Processor cores in a heterogeneous multi-core IC execute different tasks or software programs simultaneously and temporarily store information in internal memory blocks. Each memory block has an associated BIST engine to test it for malfunctions. Different memory blocks may have BIST engines of different architectures. While testing the BIST engines, an external testing apparatus is connected to the IC by way of input and output (I/O) debug ports. The external testing apparatus includes a combination of hardware and/or software that tests the operation of a corresponding processor core. The external testing apparatus provides input data at the input debug port and based on the received input data, the BIST engines from selected processor cores are initiated and the corresponding memory blocks are tested. Upon completion, output test data is generated at the output debug port and provided to the external testing apparatus. The output test data is checked with the required specifications to determine whether there are any faults in any of the memory blocks.
Since it is necessary to test multiple memory blocks across multiple cores simultaneously, debug access to multiple BIST engines with different architectures is required. Further, each multiple core exhibits different operating characteristics and unauthenticated access to any of the multiple cores may cause damage to hardware and/or software elements of the core. Therefore, it is necessary to have secure debug access to the cores.
In addition, existing multi-core IC configurations require each BIST engine with a different architecture to be tested one at a time, which significantly increases test time. Multiple memory blocks with the same BIST architecture can be tested concurrently; however, testing multiple memory blocks with different BIST architectures is a time consuming and cumbersome task that significantly increases the overall memory testing time.
It would therefore be advantageous to have a test system for concurrently testing memory blocks with BIST engines of different architectures in a multi-core IC. It would further be advantageous to have a system for testing a multi-core IC that reduces test time and cost, provides secure access to multiple processor cores for testing, and eliminates the above mentioned shortcomings of existing test systems.